Memory storage capacities of EEPROM and flash memories are being made larger to meet increasing memory requirements. Typically, EEPROM and flash memory devices are available in a single chip or single package configuration. The typical memory device integrated circuit package contains a memory array, a memory controller or microcontroller, and other circuits to, for example, address, program, and erase memory cells within the memory array.
Communications between a computer system and memory elements associated with the computer system are typically performed using a standardized communication bus. For example, when EEPROM or flash memories are used as an onboard ROM device an industry standard high speed communication bus is typically used. When EEPROM or flash memories are used as a portable storage device for a computer system, a communication bus such as a USB is used. In an additional example, when EEPROM or flash memories are used to store audio files, graphics, pictures, and video for a still camera, video camera, or portable audio device, a variety of standardized interfaces are associated with the user device.
Referring to FIG. 1, a typical prior art scheme for interfacing a memory device to a host interface is shown, as described in U.S. Pat. No. 4,731,737 by Witt et al. entitled “High Speed Intelligent Distributed Control Memory System.” A host interface circuit 52 is coupled to a plurality of memory devices 62. An interface 72 includes a clock signal line, a reset line, a read enable line, a write enable line, a chip select line, a status line, a done line and a data interface.
Each memory element in the memory array described by Witt is capable of transferring data between adjacent memory elements during a read operation or during a write operation. However, Witt does not address specific needs for certain memory structures where it is desirable to reduce or minimize control logic or control circuits contained within the memory device chip and minimize a number of pins read by the host interface circuit 52. Also, Witt does not address special needs or signaling that may be advantageous when using nonvolatile memory devices or memory devices other than RAM memory.